Western Digital announced at the RISC-V Summit three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem.
In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.
Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital’s RISC-V SweRV Core is a 32-bit, 9 stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs. It is a compact, in-order core and runs at 4.9 CoreMarks/Mhz. Its power-efficient design offers clock speeds of up to 1.8Ghz on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs.
Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.
You can find a repository contains the SweRV CoreTM design RTL on GitHub.